322 lines
11 KiB
BibTeX
322 lines
11 KiB
BibTeX
@string{mcmc = "Proc. IEEE Multi-Chip Module Conf."}
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@string{lped = "Proc. Int. Symp. on Low Power Electronics and Design"}
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@string{iccad = "Proc. Int. Conf. on Computer Aided Design"}
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@string{eurodac = "Proc. European Design Automation Conf."}
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@string{edtc = "Proc. European Design and Test Conf."}
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@string{aspdac = "Proc. Asia South Pacific Design Automation Conf."}
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@string{dac = "Proc. Design Automation Conf"}
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@string{iccd = "Proc. IEEE Int. Conf. on Computer Design"}
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@string{todaes = "ACM Trans. on Design Automation of Electronics Systems"}
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@string{tcad = "IEEE Trans. on Computer-Aided Design of Integrated Circuits andSystems"}
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@string{tcs = "IEEE Trans. on Circuits and Systems"}
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@string{tvlsi = "IEEE Trans. on Very Large Scale Integration (VLSI) Systems"}
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@string{tcomp = "IEEE Trans. on Computers"}
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@string{integration = "Integration, the VLSI Journal"}
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@string{iscas = "Proc. IEEE Int. Symp. on Circuits and Systems"}
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@string{ispd = "Proc. Int. Symp. on Physical Design"}
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@string{uclacsd = "UCLA CS Dept"}
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@string{iwrsp="Int. Workshop on Rapid System Prototyping"}
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@string{iretec="IRE Trans. on Electronic Computers"}
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@string{algorithmica="Algorithmica"}
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@string{ieepcds="IEEE Proc.-Circuits Devices Syst."}
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@string{ipl="Information Processing Letters"}
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@string{icvlsi="Int'l Conf. on VLSI Design"}
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@string{mcmc = "Proc. IEEE Multi-Chip Module Conf."}
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@string{lped = "Proc. Int. Symp. on Low Power Electronics and Design"}
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@string{iccad = "Proc. Int. Conf. on Computer Aided Design"}
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@string{eurodac = "Proc. European Design Automation Conf."}
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@string{edtc = "Proc. European Design and Test Conf."}
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@string{aspdac = "Proc. Asia South Pacific Design Automation Conf."}
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@string{dac = "Proc. Design Automation Conf"}
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@string{iccd = "Proc. IEEE Int. Conf. on Computer Design"}
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@string{todaes = "ACM Trans. on Design Automation of Electronics Systems"}
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@string{tcad = "IEEE Trans. on Computer-Aided Design of Integrated Circuits andSystems"}
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@string{tcs = "IEEE Trans. on Circuits and Systems"}
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@string{tvlsi = "IEEE Trans. on Very Large Scale Integration (VLSI) Systems"}
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@string{tcomp = "IEEE Trans. on Computers"}
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@string{integration = "Integration, the VLSI Journal"}
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@string{iscas = "Proc. IEEE Int. Symp. on Circuits and Systems"}
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@string{ispd = "Proc. Int. Symp. on Physical Design"}
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@string{uclacsd = "UCLA CS Dept"}
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@string{mcmc = "Proc. IEEE Multi-Chip Module Conf."}
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@string{lped = "Proc. Int. Symp. on Low Power Electronics and Design"}
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@string{iccad = "Proc. Int. Conf. on Computer Aided Design"}
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@string{eurodac = "Proc. European Design Automation Conf."}
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@string{edtc = "Proc. European Design and Test Conf."}
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@string{aspdac = "Proc. Asia South Pacific Design Automation Conf."}
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@string{dac = "Proc. Design Automation Conf"}
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@string{iccd = "Proc. IEEE Int. Conf. on Computer Design"}
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@string{todaes = "ACM Trans. on Design Automation of Electronics Systems"}
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@string{tcad = "IEEE Trans. on Computer-Aided Design of Integrated Circuits andSystems"}
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@string{tcs = "IEEE Trans. on Circuits and Systems"}
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@string{tvlsi = "IEEE Trans. on Very Large Scale Integration (VLSI) Systems"}
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@string{tcomp = "IEEE Trans. on Computers"}
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@string{integration = "Integration, the VLSI Journal"}
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@string{iscas = "Proc. IEEE Int. Symp. on Circuits and Systems"}
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@string{ispd = "Proc. Int. Symp. on Physical Design"}
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@string{uclacsd = "UCLA CS Dept"}
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@string{mcmc = "Proc. IEEE Multi-Chip Module Conf."}
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@string{lped = "Proc. Int. Symp. on Low Power Electronics and Design"}
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@string{iccad = "Proc. Int. Conf. on Computer Aided Design"}
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@string{eurodac = "Proc. European Design Automation Conf."}
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@string{edtc = "Proc. European Design and Test Conf."}
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@string{aspdac = "Proc. Asia South Pacific Design Automation Conf."}
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@string{dac = "Proc. Design Automation Conf"}
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@string{iccd = "Proc. IEEE Int. Conf. on Computer Design"}
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@string{todaes = "ACM Trans. on Design Automation of Electronics Systems"}
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@string{tcad = "IEEE Trans. on Computer-Aided Design of Integrated Circuits andSystems"}
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@string{tcs = "IEEE Trans. on Circuits and Systems"}
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@string{tvlsi = "IEEE Trans. on Very Large Scale Integration (VLSI) Systems"}
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@string{tcomp = "IEEE Trans. on Computers"}
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@string{integration = "Integration, the VLSI Journal"}
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@string{iscas = "Proc. IEEE Int. Symp. on Circuits and Systems"}
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@string{ispd = "Proc. Int. Symp. on Physical Design"}
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@string{uclacsd = "UCLA CS Dept"}
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@string{mcmc = "Proc. IEEE Multi-Chip Module Conf."}
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@string{lped = "Proc. Int. Symp. on Low Power Electronics and Design"}
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@string{iccad = "Proc. Int. Conf. on Computer Aided Design"}
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@string{eurodac = "Proc. European Design Automation Conf."}
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@string{edtc = "Proc. European Design and Test Conf."}
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@string{aspdac = "Proc. Asia South Pacific Design Automation Conf."}
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@string{dac = "Proc. Design Automation Conf"}
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@string{iccd = "Proc. IEEE Int. Conf. on Computer Design"}
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@string{todaes = "ACM Trans. on Design Automation of Electronics Systems"}
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@string{tcad = "IEEE Trans. on Computer-Aided Design of Integrated Circuits andSystems"}
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@string{tcs = "IEEE Trans. on Circuits and Systems"}
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@string{tvlsi = "IEEE Trans. on Very Large Scale Integration (VLSI) Systems"}
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@string{tcomp = "IEEE Trans. on Computers"}
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@string{integration = "Integration, the VLSI Journal"}
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@string{iscas = "Proc. IEEE Int. Symp. on Circuits and Systems"}
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@string{ispd = "Proc. Int. Symp. on Physical Design"}
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@string{uclacsd = "UCLA CS Dept"}
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@conference{AlDe97:segment,
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author="C. J. Alpert and A. Devgan",
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title="Wire Segmenting for Improved Buffer Insertion",
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booktitle=dac,
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year=1997,
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note="to appear",
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}
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@conference{AlHH93:ahhk,
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title="A Direct Combination of the {P}rim and {D}ijkstra Constructions for Improved Performance-Driven Global Routing",
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author="Alpert, C. J. and Hu, T. C. and Huang, J. H. and Kahng, A. B.",
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booktitle=iscas,
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year=1993,
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pages="1869--1872",
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}
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@conference{AlHK97,
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author="C. J. Alpert and J.-H. Huang and A. B. Kahng",
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title="Multilevel Circuit Partitioning",
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booktitle=dac,
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pages="530-533",
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year=1997,
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}
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@article{AlKa95,
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author="C. J. Alpert and A. B. Kahng",
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title="Recent Directions in Netlist Partitioning: A Survey",
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journal=integration,
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pages="1-81",
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year=1995,
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}
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@conference{Alpert98,
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author="C. J. Alpert",
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title="The ISPD98 Circuit Benchmark Suite",
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booktitle=ispd,
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pages="80-85",
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year=1998,
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}
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@conference{AoKu83:route,
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author="K. Aoshima and E. S. Kuh",
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title="Multi-Channel Optimization in Gate-Array LSI Layout",
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booktitle=iscas,
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year=1983,
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pages="1005-1008",
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}
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@conference{AwBP90:communication,
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author="B. Awerbuch and A. Baratz and D. Peleg",
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title="Cost-Sensitive Analysis of Communication Protocols",
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booktitle="Proc. ACM Symp. Principles of Distributed Computing",
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year=1990,
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pages="177-187",
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}
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@book{Ba90:interconnect,
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title="Circuits, Interconnections, and Packaging for {VLSI}",
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author="Bakoglu, H. B.",
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publisher="Addison-Wesley",
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year=1990,
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}
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@conference{BaWM86:htree,
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title="A Symmetric Clock-Distribution Tree and Optimized High-Speed Interconnections for Reduced Clock Skew in {ULSI} and {WSI} Circuits",
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author="Bakoglu, H. B. and Walker, J. T. and Meindl, J. D.",
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booktitle=iccd,
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year=1986,
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pages="118-122",
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}
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@article{Be88:steiner,
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author="M. W. Bern",
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title="Two Probabilistic Results on Rectilinear {Steiner} Trees",
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journal=Algorithmica,
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year=1988,
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volume=3,
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pages="191-204",
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}
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@conference{BeBJ94:sizing,
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author="M. Berkelaar and P. Buurman and J. Jess",
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title="Computing the Entire Active Area/Power Consumption versus Delay Trade-off Curve for Gate Sizing with a Piecewise Linear Simulator",
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booktitle=iccad,
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year=1994,
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pages="474-480",
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}
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@conference{BeJe90:sizing,
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title="Gate Sizing in {MOS} Digital Circuits with Linear Programming",
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author="Berkelaar, M. and Jess, J.",
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booktitle=eurodac,
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year=1990,
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pages="217-221",
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}
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@conference{BoCK92:resistratio,
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title="On High-Speed VLSI Interconnects: Analysis and Design",
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author="K. D. Boese and J. Cong and A. B. Kahng and K. S. Leung and D. Zhou",
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booktitle="Proc. Asia-Pacific Conf. on Circuits and Systems",
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year=1992,
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pages="35-40",
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}
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@conference{BoKM93:fidelity,
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title="Fidelity and Near-Optimality of {E}lmore-Based Routing Constructions",
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author="Boese, K. D. and Kahng, A. B. and McCoy, B. A. and Robins, G.",
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booktitle=iccd,
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year=1993,
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pages="81-84",
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}
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@conference{BoKM94:sert,
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title="Rectilinear {S}teiner Trees with Minimum {E}lmore Delay",
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author="Boese, K. D. and Kahng, A. B. and McCoy, B. A. and Robins, G.",
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booktitle=dac,
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year=1994,
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pages="381-386",
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}
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@article{BoKM95:sert,
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title="Near-Optimal Critical Sink Routing Tree Constructions",
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author="Boese, K. D. and Kahng, A. B. and McCoy, B. A. and Robins, G.",
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journal=tcad,
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volume=14,
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number=12,
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pages="1417-1436",
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year=1995,
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month=dec,
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}
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@conference{BoKR93:csrt,
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title="High-performance routing trees with identified critical sinks",
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author="Boese, K. D. and Kahng, A. B. and Robins, G.",
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booktitle=dac,
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year=1993,
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pages="182-187",
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}
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@conference{BoKa92:zero,
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title="Zero-Skew Clock Routing Trees With Minimum Wirelength",
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author="Boese, K. D. and Kahng, A. B.",
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booktitle="Proc. IEEE Int. ASIC Conf.",
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year=1992,
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month=sep,
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pages="1.1.1-1.1.5",
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}
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@article{BoOI94:edge,
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title="An Edge-Based Heuristic for {S}teiner Routing",
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author="Borah, M. and Owens, R. M. and Irwin, M. J.",
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journal=tcad,
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volume=13,
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number=12,
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year=1994,
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month=dec,
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pages="1563-1568",
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}
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@conference{BoOI95:sizing,
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author="M. Borah and R. M. Owens and M. J. Irwin",
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title="Transistor Sizing for Minimizing Power Consumption of {CMOS} Circuit under Delay Constraint",
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booktitle="Proc. Int. Symp. on Lower Power Design",
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year=1995,
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pages="167-172",
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}
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@article{BoOI96:sizing,
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author="M. Borah and R. M. Owens and M. J. Irwin",
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title="Transistor Sizing for Low Power {CMOS} Circuits",
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journal=tcad,
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year=1996,
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month=jun,
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volume=15,
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number=6,
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pages="665-671",
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}
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@article{Br86:obdd,
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title="Graph-based algorithms for Boolean function Manipulation",
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author="Bryant, R.E.",
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journal=tcomp,
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volume="C-35",
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number=8,
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pages="677-691",
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}
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@conference{BrBK89:benchmark,
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title="Combinational Profiles of Sequential Benchmark Circuits",
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author="Brglez, F. and Bryan, D. and Kozminski, K.",
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booktitle=iscas,
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year=1989,
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pages="1929-1934",
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}
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@conference{BrBa90:phigure,
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author="R. J. Brouwer and P. Banerjee",
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title="PHIGURE: A Parallel Hierarchical Global Router",
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booktitle=dac,
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year=1990,
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pages="650-653",
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}
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@conference{Breuer77,
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author="M. A. Breuer",
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title="A Class of Min-Cut Placement Algorithms",
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booktitle=dac,
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pages="284-290",
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year=1997,
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}
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@article{BuP83:hierarchical,
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author="M. Burstein and R. Pelavin",
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title="Hierarchical Wire Routing",
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journal=tcad,
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volume="CAD-2",
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number=4,
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month=October,
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year=1983,
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pages="223-234",
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}
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@conference{CaCh91:flow,
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author="R. C. Carden and C.-K. Cheng",
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title="A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm",
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booktitle=dac,
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year=1991,
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pages="316-321",
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}
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