initial commit of bin scripts into git

2023-11-08 13:38:19 +11:00
commit 3735eea3c6
113 changed files with 11631 additions and 0 deletions
--- a/tkbib1.0/sample.bib
+++ b/tkbib1.0/sample.bib
@@ -0,0 +1,321 @@
+@string{mcmc = "Proc. IEEE Multi-Chip Module Conf."}
+@string{lped = "Proc. Int. Symp. on Low Power Electronics and Design"}
+@string{iccad = "Proc. Int. Conf. on Computer Aided Design"}
+@string{eurodac = "Proc. European Design Automation Conf."}
+@string{edtc = "Proc. European Design and Test Conf."}
+@string{aspdac = "Proc. Asia South Pacific Design Automation Conf."}
+@string{dac = "Proc. Design Automation Conf"}
+@string{iccd = "Proc. IEEE Int. Conf. on Computer Design"}
+@string{todaes = "ACM Trans. on Design Automation of Electronics Systems"}
+@string{tcad = "IEEE Trans. on Computer-Aided Design of Integrated Circuits andSystems"}
+@string{tcs = "IEEE Trans. on Circuits and Systems"}
+@string{tvlsi = "IEEE Trans. on Very Large Scale Integration (VLSI) Systems"}
+@string{tcomp = "IEEE Trans. on Computers"}
+@string{integration = "Integration, the VLSI Journal"}
+@string{iscas = "Proc. IEEE Int. Symp. on Circuits and Systems"}
+@string{ispd = "Proc. Int. Symp. on Physical Design"}
+@string{uclacsd = "UCLA CS Dept"}
+@string{iwrsp="Int. Workshop on Rapid System Prototyping"}
+@string{iretec="IRE Trans. on Electronic Computers"}
+@string{algorithmica="Algorithmica"}
+@string{ieepcds="IEEE Proc.-Circuits Devices Syst."}
+@string{ipl="Information Processing Letters"}
+@string{icvlsi="Int'l Conf. on VLSI Design"}
+@string{mcmc = "Proc. IEEE Multi-Chip Module Conf."}
+@string{lped = "Proc. Int. Symp. on Low Power Electronics and Design"}
+@string{iccad = "Proc. Int. Conf. on Computer Aided Design"}
+@string{eurodac = "Proc. European Design Automation Conf."}
+@string{edtc = "Proc. European Design and Test Conf."}
+@string{aspdac = "Proc. Asia South Pacific Design Automation Conf."}
+@string{dac = "Proc. Design Automation Conf"}
+@string{iccd = "Proc. IEEE Int. Conf. on Computer Design"}
+@string{todaes = "ACM Trans. on Design Automation of Electronics Systems"}
+@string{tcad = "IEEE Trans. on Computer-Aided Design of Integrated Circuits andSystems"}
+@string{tcs = "IEEE Trans. on Circuits and Systems"}
+@string{tvlsi = "IEEE Trans. on Very Large Scale Integration (VLSI) Systems"}
+@string{tcomp = "IEEE Trans. on Computers"}
+@string{integration = "Integration, the VLSI Journal"}
+@string{iscas = "Proc. IEEE Int. Symp. on Circuits and Systems"}
+@string{ispd = "Proc. Int. Symp. on Physical Design"}
+@string{uclacsd = "UCLA CS Dept"}
+@string{mcmc = "Proc. IEEE Multi-Chip Module Conf."}
+@string{lped = "Proc. Int. Symp. on Low Power Electronics and Design"}
+@string{iccad = "Proc. Int. Conf. on Computer Aided Design"}
+@string{eurodac = "Proc. European Design Automation Conf."}
+@string{edtc = "Proc. European Design and Test Conf."}
+@string{aspdac = "Proc. Asia South Pacific Design Automation Conf."}
+@string{dac = "Proc. Design Automation Conf"}
+@string{iccd = "Proc. IEEE Int. Conf. on Computer Design"}
+@string{todaes = "ACM Trans. on Design Automation of Electronics Systems"}
+@string{tcad = "IEEE Trans. on Computer-Aided Design of Integrated Circuits andSystems"}
+@string{tcs = "IEEE Trans. on Circuits and Systems"}
+@string{tvlsi = "IEEE Trans. on Very Large Scale Integration (VLSI) Systems"}
+@string{tcomp = "IEEE Trans. on Computers"}
+@string{integration = "Integration, the VLSI Journal"}
+@string{iscas = "Proc. IEEE Int. Symp. on Circuits and Systems"}
+@string{ispd = "Proc. Int. Symp. on Physical Design"}
+@string{uclacsd = "UCLA CS Dept"}
+@string{mcmc = "Proc. IEEE Multi-Chip Module Conf."}
+@string{lped = "Proc. Int. Symp. on Low Power Electronics and Design"}
+@string{iccad = "Proc. Int. Conf. on Computer Aided Design"}
+@string{eurodac = "Proc. European Design Automation Conf."}
+@string{edtc = "Proc. European Design and Test Conf."}
+@string{aspdac = "Proc. Asia South Pacific Design Automation Conf."}
+@string{dac = "Proc. Design Automation Conf"}
+@string{iccd = "Proc. IEEE Int. Conf. on Computer Design"}
+@string{todaes = "ACM Trans. on Design Automation of Electronics Systems"}
+@string{tcad = "IEEE Trans. on Computer-Aided Design of Integrated Circuits andSystems"}
+@string{tcs = "IEEE Trans. on Circuits and Systems"}
+@string{tvlsi = "IEEE Trans. on Very Large Scale Integration (VLSI) Systems"}
+@string{tcomp = "IEEE Trans. on Computers"}
+@string{integration = "Integration, the VLSI Journal"}
+@string{iscas = "Proc. IEEE Int. Symp. on Circuits and Systems"}
+@string{ispd = "Proc. Int. Symp. on Physical Design"}
+@string{uclacsd = "UCLA CS Dept"}
+@string{mcmc = "Proc. IEEE Multi-Chip Module Conf."}
+@string{lped = "Proc. Int. Symp. on Low Power Electronics and Design"}
+@string{iccad = "Proc. Int. Conf. on Computer Aided Design"}
+@string{eurodac = "Proc. European Design Automation Conf."}
+@string{edtc = "Proc. European Design and Test Conf."}
+@string{aspdac = "Proc. Asia South Pacific Design Automation Conf."}
+@string{dac = "Proc. Design Automation Conf"}
+@string{iccd = "Proc. IEEE Int. Conf. on Computer Design"}
+@string{todaes = "ACM Trans. on Design Automation of Electronics Systems"}
+@string{tcad = "IEEE Trans. on Computer-Aided Design of Integrated Circuits andSystems"}
+@string{tcs = "IEEE Trans. on Circuits and Systems"}
+@string{tvlsi = "IEEE Trans. on Very Large Scale Integration (VLSI) Systems"}
+@string{tcomp = "IEEE Trans. on Computers"}
+@string{integration = "Integration, the VLSI Journal"}
+@string{iscas = "Proc. IEEE Int. Symp. on Circuits and Systems"}
+@string{ispd = "Proc. Int. Symp. on Physical Design"}
+@string{uclacsd = "UCLA CS Dept"}
+@conference{AlDe97:segment,
+  author="C. J. Alpert and A. Devgan",
+  title="Wire Segmenting for Improved Buffer Insertion",
+  booktitle=dac,
+  year=1997,
+  note="to appear",
+}
+
+@conference{AlHH93:ahhk,
+  title="A Direct Combination of the {P}rim and {D}ijkstra Constructions for  Improved Performance-Driven Global Routing",
+  author="Alpert, C. J. and Hu, T. C. and Huang, J. H. and Kahng, A. B.",
+  booktitle=iscas,
+  year=1993,
+  pages="1869--1872",
+}
+
+@conference{AlHK97,
+  author="C. J. Alpert and J.-H. Huang and A. B. Kahng",
+  title="Multilevel Circuit Partitioning",
+  booktitle=dac,
+  pages="530-533",
+  year=1997,
+}
+
+@article{AlKa95,
+  author="C. J. Alpert and A. B. Kahng",
+  title="Recent Directions in Netlist Partitioning: A Survey",
+  journal=integration,
+  pages="1-81",
+  year=1995,
+}
+
+@conference{Alpert98,
+  author="C. J. Alpert",
+  title="The ISPD98 Circuit Benchmark Suite",
+  booktitle=ispd,
+  pages="80-85",
+  year=1998,
+}
+
+@conference{AoKu83:route,
+  author="K. Aoshima and E. S. Kuh",
+  title="Multi-Channel Optimization in Gate-Array LSI Layout",
+  booktitle=iscas,
+  year=1983,
+  pages="1005-1008",
+}
+
+@conference{AwBP90:communication,
+  author="B. Awerbuch and A. Baratz and D. Peleg",
+  title="Cost-Sensitive Analysis of Communication Protocols",
+  booktitle="Proc. ACM Symp. Principles of Distributed Computing",
+  year=1990,
+  pages="177-187",
+}
+
+@book{Ba90:interconnect,
+  title="Circuits, Interconnections, and Packaging for {VLSI}",
+  author="Bakoglu, H. B.",
+  publisher="Addison-Wesley",
+  year=1990,
+}
+
+@conference{BaWM86:htree,
+  title="A Symmetric Clock-Distribution Tree and Optimized High-Speed  Interconnections for Reduced Clock Skew in {ULSI} and {WSI} Circuits",
+  author="Bakoglu, H. B. and Walker, J. T. and Meindl, J. D.",
+  booktitle=iccd,
+  year=1986,
+  pages="118-122",
+}
+
+@article{Be88:steiner,
+  author="M. W. Bern",
+  title="Two Probabilistic Results on Rectilinear {Steiner} Trees",
+  journal=Algorithmica,
+  year=1988,
+  volume=3,
+  pages="191-204",
+}
+
+@conference{BeBJ94:sizing,
+  author="M. Berkelaar and P. Buurman and J. Jess",
+  title="Computing the Entire Active Area/Power Consumption versus Delay  Trade-off Curve for Gate Sizing with a Piecewise Linear Simulator",
+  booktitle=iccad,
+  year=1994,
+  pages="474-480",
+}
+
+@conference{BeJe90:sizing,
+  title="Gate Sizing in {MOS} Digital Circuits with Linear Programming",
+  author="Berkelaar, M. and Jess, J.",
+  booktitle=eurodac,
+  year=1990,
+  pages="217-221",
+}
+
+@conference{BoCK92:resistratio,
+  title="On High-Speed VLSI Interconnects: Analysis and Design",
+  author="K. D. Boese and J. Cong and A. B. Kahng and K. S. Leung and D. Zhou",
+  booktitle="Proc. Asia-Pacific Conf. on Circuits and Systems",
+  year=1992,
+  pages="35-40",
+}
+
+@conference{BoKM93:fidelity,
+  title="Fidelity and Near-Optimality of {E}lmore-Based Routing Constructions",
+  author="Boese, K. D. and Kahng,  A. B. and McCoy, B. A. and Robins, G.",
+  booktitle=iccd,
+  year=1993,
+  pages="81-84",
+}
+
+@conference{BoKM94:sert,
+  title="Rectilinear {S}teiner Trees with Minimum {E}lmore Delay",
+  author="Boese, K. D. and Kahng, A. B. and McCoy, B. A. and Robins, G.",
+  booktitle=dac,
+  year=1994,
+  pages="381-386",
+}
+
+@article{BoKM95:sert,
+  title="Near-Optimal Critical Sink Routing Tree Constructions",
+  author="Boese, K. D. and Kahng, A. B. and McCoy, B. A. and Robins, G.",
+  journal=tcad,
+  volume=14,
+  number=12,
+  pages="1417-1436",
+  year=1995,
+  month=dec,
+}
+
+@conference{BoKR93:csrt,
+  title="High-performance routing trees with identified critical sinks",
+  author="Boese, K. D. and Kahng,  A. B. and Robins, G.",
+  booktitle=dac,
+  year=1993,
+  pages="182-187",
+}
+
+@conference{BoKa92:zero,
+  title="Zero-Skew Clock Routing Trees With Minimum Wirelength",
+  author="Boese, K. D. and Kahng, A. B.",
+  booktitle="Proc. IEEE Int. ASIC Conf.",
+  year=1992,
+  month=sep,
+  pages="1.1.1-1.1.5",
+}
+
+@article{BoOI94:edge,
+  title="An Edge-Based Heuristic for {S}teiner Routing",
+  author="Borah, M. and Owens, R. M. and Irwin, M. J.",
+  journal=tcad,
+  volume=13,
+  number=12,
+  year=1994,
+  month=dec,
+  pages="1563-1568",
+}
+
+@conference{BoOI95:sizing,
+  author="M. Borah and R. M. Owens and M. J. Irwin",
+  title="Transistor Sizing for Minimizing Power Consumption of {CMOS} Circuit        under Delay Constraint",
+  booktitle="Proc. Int. Symp. on Lower Power Design",
+  year=1995,
+  pages="167-172",
+}
+
+@article{BoOI96:sizing,
+  author="M. Borah and R. M. Owens and M. J. Irwin",
+  title="Transistor Sizing for Low Power {CMOS} Circuits",
+  journal=tcad,
+  year=1996,
+  month=jun,
+  volume=15,
+  number=6,
+  pages="665-671",
+}
+
+@article{Br86:obdd,
+  title="Graph-based algorithms for Boolean function Manipulation",
+  author="Bryant, R.E.",
+  journal=tcomp,
+  volume="C-35",
+  number=8,
+  pages="677-691",
+}
+
+@conference{BrBK89:benchmark,
+  title="Combinational Profiles of Sequential Benchmark Circuits",
+  author="Brglez, F. and Bryan, D. and Kozminski, K.",
+  booktitle=iscas,
+  year=1989,
+  pages="1929-1934",
+}
+
+@conference{BrBa90:phigure,
+  author="R. J. Brouwer and P. Banerjee",
+  title="PHIGURE: A Parallel Hierarchical Global Router",
+  booktitle=dac,
+  year=1990,
+  pages="650-653",
+}
+
+@conference{Breuer77,
+  author="M. A. Breuer",
+  title="A Class of Min-Cut Placement Algorithms",
+  booktitle=dac,
+  pages="284-290",
+  year=1997,
+}
+
+@article{BuP83:hierarchical,
+  author="M. Burstein and R. Pelavin",
+  title="Hierarchical Wire Routing",
+  journal=tcad,
+  volume="CAD-2",
+  number=4,
+  month=October,
+  year=1983,
+  pages="223-234",
+}
+
+@conference{CaCh91:flow,
+  author="R. C. Carden and C.-K. Cheng",
+  title="A Global Router Using An Efficient Approximate Multicommodity  Multiterminal Flow Algorithm",
+  booktitle=dac,
+  year=1991,
+  pages="316-321",
+}
+